The present invention relates to a power supply circuit of a semiconductor integrated circuit, and particularly to a regulator circuit.
In related arts, a step-down regulator has been used in an attempt to reduce current consumption in a semiconductor internal circuit and not apply a voltage greater than or equal to the rated value of an internal power supply voltage to the internal circuit. However, there has been a problem that when the voltage supplied to the regulator is reduced, the output voltage from the regulator is reduced, the operation of the internal circuit is not stabilized. Therefore, a following configuration has generated a technique to stably supply the internal power supply voltage while reducing the power consumption. The configuration is that when an external power supply voltage exceeds the rated value of the internal power supply voltage, a voltage reduced by a regulator circuit is supplied as the internal power supply voltage, while when the external power supply voltage is less than or equal to the rated value of the internal power supply voltage, the regulator circuit is deactivated and the internal power supply voltage is directly supplied by an external power supply line. A related art is disclosed in Japanese Unexamined Patent Application Publication No. 2000-339042.
Japanese Unexamined Patent Application Publication No. 2000-339042 aims to reduce current consumption in a semiconductor integrated circuit and stably supply the internal power supply voltage, and has a feature of including a regulatory function for supplying a stabled voltage to an internal circuit from an external power supply that is supplied to the semiconductor integrated circuit. Specifically, when the external power supply voltage exceeds the rated value of the internal power supply voltage, the voltage reduced by the regulator circuit is supplied as the internal power supply voltage. When the external power supply voltage is less than or equal to the rated value of the internal power supply voltage, the regulator circuit is deactivated and the internal power supply voltage is directly supplied by the external power supply line.
FIG. 8 shows a configuration of a voltage generation circuit disclosed in Japanese Unexamined Patent Application Publication No. 2000-339042. A voltage generation circuit 100p includes an external power supply line 10p to which an external power supply voltage VCE is transmitted, an internal power supply line 20p for supplying an internal power supply voltage Vcc to a load, a regulator circuit 30p that has the external power supply line 10p as an internal terminal and outputs 3.3 V, which is the rated value of the internal power supply voltage Vcc, from an output terminal, and a voltage switching transistor 50p that is activated according to a voltage level of a node Na and connects the external power supply line 10p and the internal power supply line 20p. 
The regulator circuit 30p further includes an output control terminal CNT. When an H-level signal is input to the output control terminal CNT, the regulator circuit 30p is deactivated and stops generating the output voltage (3.3 V) to the output terminal OUT. Accordingly, one of the regulator circuit 30p and the voltage switching transistor 50p is complementarily activated according to the voltage level of the node Na.
The voltage generation circuit 100p further includes a comparator 40p for determining the voltage level of Na according to the external power supply voltage VCE. The comparator 40p outputs the H level to the node Na when the external power supply voltage VCE is greater than a reference voltage V1. The comparator 40p is composed of a differential amplifier circuit and the like using an operational amplifier. The reference voltage V1 may be set to a voltage greater than the rated value of the internal power supply voltage Vcc and also less than a peak value of the external power supply voltage. In FIG. 6, the reference voltage is set to 3.9 V, for example. The voltage generation circuit 100p further includes capacitors Ci and Co for stabilizing the voltage of the external power supply line 10p and the internal power supply line 20p. 
In the voltage generation circuit 100p, when the external power supply voltage VCE is 3.3 V (≦V1:V1 or less), the external power supply line 10p and the internal power supply line 20p are connected by turning on the voltage switching transistor 50p while deactivating the regulator circuit 30p and stopping from generating an output voltage by lowering the voltage of the node Na to the L level by the comparator 40p. Then, when the external power supply voltage VCE is 3.3 V, the internal power supply voltage is directly supplied to the internal power supply line 20p by the external power supply line 10p. 
On the other hand, when the external power supply voltage VCE is 5 V (≧V1:V1 or greater), the H-level voltage is output to the node Na by the comparator 40p. This activates the operation of the regulator circuit 30p while turning off the voltage switching transistor 50p. Accordingly, when the external power supply voltage VCE is 5 V, the internal power supply line 20p and the external power supply line 10p are blocked and the output voltage from the regulator circuit 30p is supplied to the internal power supply line 20p. 
As described above, the following configuration enables the voltage generation circuit 100p to stably supply the internal power supply voltage while reducing the entire power consumption. The configuration is that when the external power supply voltage exceeds the rated value of the internal power supply voltage, the voltage reduced by the regulator circuit is supplied as the internal power supply voltage. When the external power supply voltage is the rated value of the internal power supply voltage, the regulator circuit is deactivated and the internal power supply voltage is directly supplied from the external power supply line.
However, there lies a problem in the technique disclosed in Japanese Unexamined Patent Application Publication No. 2000-339042 that the output voltage from the regulator could easily fluctuate when switching between the step-down regulator and the means to directly supply the internal power supply voltage from the external power supply line. In other words, there is a problem that a fluctuation is generated in the output voltage from the regulator by the fluctuation in the external power supply voltage. The reason is that as the regulator circuit 30p and the voltage switching transistor 50p are complementarily activated according to the voltage level of the node Na, when the external power supply voltage VCE is less than the reference voltage V1, for example, a time lag is generated since the voltage switching transistor 50p is turned off until the regulator circuit 30p is activated, and thereby fluctuating the internal power supply voltage Vcc.
For this problem, the technique disclosed in Japanese Unexamined Patent Application Publication No. 2000-339042 includes a stabilizing capacity as an output external component of the regulator circuit and this enables suppression of fluctuation in the output voltage. On the other hand, the stabilizing capacity as the output external component has a disadvantage such as an increase in the device cost due to reservation of an area on the mounting substrate and mounting components.